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PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
Rev. 03 -- 3 December 2008 Product data sheet
1. General description
The PCA9701/PCA9702 are low power 18 V tolerant SPI General Purpose Input (GPI) shift register designed to monitor the status of switch inputs. It generates an interrupt when one or more of the switch inputs change state. The input level is recognized as a HIGH when it is greater than 0.7 x VDD and as a LOW when it is less than 0.4 x VDD (minimum threshold of 2 V at 5 V node). The PCA9701 can monitor up to 16 switch inputs and the PCA9702 can monitor up to 8 switch inputs. The falling edge of the CS pin samples the input port status and clears the interrupt. When CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of the shift register. The serial input is sampled on the falling edge of SCLK. Each of the input ports has a 18 V breakdown ESD protection circuit. When used with a series resistor (minimum 100 k), the input can connect to a 12 V battery and support double battery, reverse battery, 27 V jump start and 40 V load dump conditions in automotive applications. Higher voltages can be tolerated on the inputs depending on the series resistor used to limit the input current. With both the high breakdown voltage and high ESD, these devices are useful for both automotive (AEC-Q100 qualification available) and mobile applications. The PCA9703/PCA9704 are new pin compatible devices for the PCA9701/PCA9702 which have an interrupt masking feature allowing selected inputs to not generate interrupts and provides higher ground offset of 0.55 x VDD (minimum of 2.5 V at 5 V node) with minimum hysteresis of 0.05 x VDD (minimum of 225 mV at 5 V node).
2. Features
I 16 general purpose input ports (PCA9701) or 8 general purpose input ports (PCA9702) I 18 V tolerant input ports with 100 k external series resistor I Input LOW threshold 0.4 x VDD with minimum of 2 V at VDD = 4.5 V I Open-drain interrupt output I Interrupt enable pin (INT_EN) disables interrupt output I VDD range: 2.5 V to 5.5 V I IDD is very low 2.5 A maximum I SPI serial interface with speeds up to 5 MHz I AEC-Q100 qualification available I ESD protection exceeds 8 kV HBM per JESD22-A114, 350 V MM per AEC-Q100, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
I Operating temperature range: -40 C to +125 C I PCA9701 offered in SO24, TSSOP24 and HWQFN24 packages I PCA9702 offered in TSSOP16 package
3. Applications
I I I I I I Body control modules Switch monitoring Industrial equipment Cellular telephones Emergency lighting SBC wake pin extension
4. Ordering information
Table 1. Ordering information Topside mark PCA9701D 9701 Package Name SO24 Description plastic small outline package; 24 leads; body width 7.5 mm Version SOT137-1 SOT994-1 SOT355-1 SOT355-1 SOT403-1 Type number PCA9701D PCA9701HF PCA9701PW PCA9701PW/Q100[1] PCA9702PW
HWQFN24 plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm
PCA9701PW TSSOP24 PCA9701/Q PCA9702 TSSOP24 TSSOP16
[1]
PCA9701PW/Q100 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
2 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
5. Block diagram
VDD
PCA9701/PCA9702
INT
IN0
DFF0
INT_EN
IN1
DFF1 SHIFT REGISTER
INn(1)
DFFn(1) INPUT STATUS REGISTER
SDOUT SDIN SCLK CS
20 A
VSS
002aac422
(1) n = 15 for PCA9701; n = 7 for PCA9702
Fig 1. Block diagram of PCA9701; PCA9702
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
3 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
6. Pinning information
6.1 Pinning
SDOUT INT INT_EN IN0 IN1 IN2 IN3 IN4 IN5
1 2 3 4 5 6 7 8 9
24 VDD 23 SDIN 22 SCLK 21 CS 20 IN15 19 IN14 18 IN13 17 IN12 16 IN11 15 IN10 14 IN9 13 IN8
002aac636
SDOUT INT INT_EN IN0 IN1 IN2 IN3 IN4 IN5
1 2 3 4 5 6 7 8 9
24 VDD 23 SDIN 22 SCLK 21 CS 20 IN15 19 IN14 18 IN13 17 IN12 16 IN11 15 IN10 14 IN9 13 IN8
002aac424
PCA9701D
PCA9701PW PCA9701PW/Q100
IN6 10 IN7 11 VSS 12
IN6 10 IN7 11 VSS 12
Fig 2. Pin configuration for SO24
24 INT_EN 22 SDOUT
Fig 3. Pin configuration for TSSOP24
terminal 1 index area IN0 IN1 IN2 IN3 IN4 IN5 1 2 3 4 5 6
19 SCLK 18 CS 17 IN15 SDOUT INT INT_EN IN0 IN1 IN2 IN3
002aad050
20 SDIN
21 VDD
23 INT
1 2 3 4 5 6 7 8
002aac425
16 VDD 15 SDIN 14 SCLK 13 CS 12 IN7 11 IN6 10 IN5 9 IN4
PCA9701HF
16 IN14 15 IN13 14 IN12 13 IN11
PCA9702PW
IN8 10
IN9 11
IN10 12
7
8 IN7
IN6
VSS
9
VSS
Transparent top view
Fig 4. Pin configuration for HWQFN24
Fig 5. Pin configuration for TSSOP16
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
4 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
6.2 Pin description
Table 2. Symbol SDOUT INT INT_EN Pin description Pin SO24, TSSOP24 1 2 3 HWQFN24 TSSOP16 22 23 24 1 2 3 output output input 3-state serial data output; normally high-impedance open-drain interrupt output (active LOW) interrupt output enable 1 = interrupt is enabled 0 = interrupt is disabled and high-impedance IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 VSS IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 CS SCLK SDIN VDD
[1]
Type
Description
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9[1] 10 11 12 13 14 15 16 17 18 19 20 21
4 5 6 7 9 10 11 12 8 13 14 15 16
input input input input input input input input ground input input input input input input input input input input input supply
input port 0 input port 1 input port 2 input port 3 input port 4 input port 5 input port 6 input port 7 ground supply input port 8 input port 9 input port 10 input port 11 input port 12 input port 13 input port 14 input port 15 chip select (active LOW) serial input clock serial data input (20 A pull-down) supply voltage
HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
5 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
7. Functional description
PCA9701 is a 16-bit General Purpose Input (GPI) with an open-drain interrupt output designed to monitor switch status. By putting an external 100 k series resistor at the input port, the device allows the input to tolerate momentary double 12 V battery, reverse battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted when an input port status changes. The open-drain interrupt output is enabled when INT_EN is HIGH and disabled when INT_EN is LOW. The input port status is accessed via the 4-wire SPI interface. The PCA9702 is the 8-bit version of the PCA9701. Multiple PCA9701 or PCA9702 devices can be serially connected for monitoring a large number of switches by connecting the SDOUT of one device to the SDIN of the next device. SCLK and CS must be common among all devices and interrupt outputs may be tied together. No external logic is necessary because all the devices' interrupt outputs are open-drain that function as `wired-AND' and can simply be connected together to a single pull-up resistor.
7.1 SPI bus operation
The PCA9701 or PCA9702 interfaces with the controller via the 4-wire SPI bus that is comprised of the following signals: chip select (CS), serial clock (SCLK), serial data in (SDIN), and serial data out (SDOUT). To access the device, the controller asserts CS LOW, then sends SCLK and SDIN. When reading/writing is complete, the controller de-asserts CS. See Figure 6 for register access timing.
7.1.1 CS - chip select
The CS pin is the device chip select and is an active LOW input. The falling edge of CS captures the input port status in the input status register. If the interrupt output is asserted, the falling edge of CS will clear the interrupt. When CS is LOW, the SPI interface is active. When CS is HIGH, the SPI interface is disabled.
7.1.2 SCLK - serial clock input
SCLK is the serial clock input to the device. It should be LOW and remain LOW during the falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel loads the shift register from the input. The subsequent rising edges on SCLK serially shifts data out from the shift register. The falling edge of SCLK samples the data on SDIN.
7.1.3 SDIN - serial data input
SDIN is the serial data input port. The data is sampled into the shift register on the falling edge of SCLK. SDIN is only active when CS is LOW. This input has a 20 A pull-down current source.
7.1.4 SDOUT - serial data output
SDOUT is the serial data output signal. SDOUT is high-impedance when CS is HIGH and switches to low-impedance after CS goes LOW. When CS is LOW, after the first rising edge of SCLK the most significant bit in the shift register is presented on SDOUT. Subsequent rising edges of SCLK shift the remaining data from the shift register onto SDOUT.
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
6 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
7.1.5 Register access timing
Figure 6 shows the waveforms of the device operation. Initially CS is HIGH and SCLK is LOW. On the falling edge of CS, input port status, DATA[n:0] is captured into the input status register, and subsequently the first rising edge of SCLK parallel loads the shift register. The falling edge of SCLK samples the data on the SDIN. The MSB from the shift register is valid and available on the SDOUT after the first rising edge of SCLK.
sample SDIN CS
SCLK
SDIN
MSB in
MSB - 1 in
LSB in
high-impedance SDOUT MSB out
MSB - 1 out
LSB out
shift register
DATA[n:0]
input status register
DATA[n:0]
002aac426
DATA[n:0] is data on the input pins, IN[n:0]. For 8-bit GPI (PCA9702), n = 7; for 16-bit GPI (PCA9701), n = 15. Shaded areas indicate active but invalid data.
Fig 6. Register access timing
7.2 Interrupt output
INT is the open-drain interrupt output and is active LOW. A pull-up resistor of approximately 10 k is recommended. The interrupt output is asserted when the input status is changed, and is cleared on the falling edge of CS or when the input port status matches the input status register. When there are multiple devices, the INT outputs may be tied together to a single pull-up. Table 3 illustrates the state of the interrupt output versus the state of the input port and input status register. The interrupt output is asserted when the input port and input status register differ.
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
7 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
Table 3. Interrupt output function truth table H = HIGH; L = LOW; X = don't care INT_EN H H H H L
[1] [2]
Input port status L L H H X
Input status register[1] L H L H X
INT output[2] H L L H H
Input status register is the value or content of the D flip-flops. Logic states shown for INT pin assumes 10 k pull-up resistor.
7.3 General Purpose Inputs
The General Purpose Inputs (GPI) are designed to behave like a typical input in the 0 V to 5.5 V range, but are also designed to have low leakage currents at elevated voltages. The input structure allows for elevated voltages to be applied through a series resistor. The series resistor is required when the input voltage is above 5.5 V. The series resistor is required for two reasons: first, to prevent damage to the input avalanche diode, and second, to prevent the ESD protection circuitry from creating an excessive current flow. The ESD protection circuitry includes a latch-back style device, which provides excellent ESD protection during assembly or typical 5.5 V applications. The series resistor limits the current flowing into the part and provides additional ESD protection. The limited current prevents the ESD latch-back device from latching back to a low voltage, which would cause excessive current flow and damage the part. The minimum required series resistance for applications with input voltages above 5.5 V is 100 k. For applications requiring an applied voltage above 27 V, Equation 1 is recommended to determine the series resistor. Failure to include the appropriate input series resistor may result in product failure and will void the warranty. voltage applied - 17 V R s = ----------------------------------------------------------II (1)
The series resistor should be placed physically as close as possible to the connected input to reduce the effective node capacitance. The input response time is effected by the RC time constant of the series resistor and the input node capacitance.
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
8 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
7.3.1 VIL, VIH and switching points
A minimum LOW threshold of 2.0 V is guaranteed for the logical switching points for the inputs. See Figure 7 for details.
VI
HIGH VDD
0.7VDD
VIH VIL hysteresis minimum possible ground shift LOW
0.4VDD
0V
002aae128
Fig 7.
Logic level thresholds for general purpose inputs
The VIL is specified as a maximum of 0.40 x VDD and is 2.0 V at 4.5 V VDD. This means that if the user applies 2.0 V or less to the input (with VDD = 4.5 V), or as the voltage passes this threshold, they will always see a LOW. The VIH is specified as a minimum of 0.7 x VDD. This means that if the user applies 3.15 V or more to the input (with VDD = 4.5 V), or as the voltage passes this threshold, they will always see a HIGH.
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
9 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8. Application design-in information
8.1 General application
2.5 V to 5.5 V
18 V
1.5 k 100 k
IN0 relay
VDD
10 k
18 V
100 k
INT CS SCLK SDIN SDOUT IN1 INT_EN
CONTROLLER OR PROCESSOR
180 V open
500 k
PCA9701/ PCA9702
IN2
50 k
5V
10 k
INn(1)
VSS
002aac423
(1) n = 15 for PCA9701; n = 7 for PCA9702
Fig 8.
Typical application
8.2 Automotive application
Supports:
* * * * *
12 V battery (8 V to 16 V) Double battery (16 V to 32 V) Reverse battery (-8 V to -16 V) Jump start (27 V for 60 seconds) Load dump (40 V)
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
10 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1 SBC wake port extension with cyclic biasing
System Basis Chips (SBC) offer many functions needed for in-vehicle networking solutions. Some of the features built into SBC are:
* * * *
Transceivers (HS-CAN, LIN 2.0) Scalable voltage regulators Watchdog timers; wake-up function Fail-safe function
For more information on SBC, refer to http://www.nxp.com/index.html#/pip/pip=[pfp=53482]|pp=[t=pfp,i=53482]. 8.2.1.1 UJA106x with PCA9701, standby
V3 alternate PVR100AD-B5V0 UJA106x
IN0 IN1
INT INT_EN
WAKE V1 GND
PCA9701
VDD VCC CSN C MOSI MISO SCLK GND
002aae016
IN15 VSS
CS SDIN SDOUT SCLK
Fig 9.
UJA106x with PCA9701 with supplied C (standby)
* * * *
PCA970x fits to SBC UJA106x and UJA107x family PCA970x can be powered by V1 of SBC Extends the SBC with 8/16 additional wake inputs C can be set to stop-mode during standby to save ECU standby current. SBC with GPI periodically monitors the wake inputs - Cyclic bias via V3 - Very low system current consumption even with clamped switches
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
11 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1.2
UJA106x with PCA9701, sleep
alternate PVR100AD-B5V0
alternate PMEM4010ND V3
UJA106x WAKE IN0 IN1 VDD INT_EN INT RSTN alternate PDTC144TU V1 GND
PCA9701
CS SDIN SDOUT SCLK VSS
VCC CSN C MOSI MISO SCLK GND
002aae017
IN15
Fig 10. UJA106x with PCA9701 with unsupplied C (sleep)
* Very low quiescent system current (50 A) due to disabled C and cyclically biasing
of switches
* Wake-up upon change of switches or upon bus traffic (CAN and LIN) * PCA970x supplied out of cyclically biased transistor regulator
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
12 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1.3
UJA107x with PCA9701, standby
BAT alternate PDTA144EU BAT
WBIAS UJA107x IN0 IN1 INT INT_EN WAKE V1 GND
PCA9701
VDD VCC CSN C MOSI MISO SCLK GND
002aae018
IN15 VSS
CS SDIN SDOUT SCLK
Fig 11. UJA107x with PCA9701 with supplied C (standby)
* UJA107x SBC provides WBIAS pin for cyclic biasing of the inputs * Compatible with UJA107x based ASSPs
8.2.2 Application examples including switches to battery
BAT BAT switch bias switch bias
IN0 IN1
IN0 IN1
PCA9701
PCA9701
clamp 15
IN15
IN15
002aae019
002aae020
Fig 12. Clamp 15 (ignition) detection
Fig 13. Switches to battery and ground with cyclic biasing
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
13 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
9. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Tamb = -40 C to +125 C, unless otherwise specified. Symbol VDD II VI Tstg Tj(max)
[1]
Parameter supply voltage input current input voltage storage temperature maximum junction temperature
Conditions IN[n:0] pins with series resistor and VI > 5.5 V, GPI pins IN[n:0]; no series resistor SPI pins operating
[1][2]
Min -0.5 -0.5 -0.5 -65 -
Max +6.0 350 +6 +6 +150 125
Unit V A V V C C
[1][2]
With GPI external series resistors, the inputs support double battery, reverse battery and load dump conditions. During double battery or load dump the input pin will drain slightly higher leakage current until the input drops to 18 V. For more detail of leakage current specification, please refer to Table 5 "Static characteristics". See Section 7.3 for series resistor requirements. n = 15 for PCA9701; n = 7 for PCA9702.
[2]
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
14 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
10. Static characteristics
Table 5. Static characteristics VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +125 C; unless otherwise specified. Symbol Supply VDD IDD VPOR VIL VIH II IIH ILI Ci IOL IOH Co VIL VIH IIH IOL supply voltage supply current power-on reset voltage[1]
[2]
Parameter
Conditions
Min 2.5
Typ 3.3 1.0 1.8 2.0 2 20 2 4
Max 5.5 2.5 2.2
Unit V A V
VDD = 5.5 V; input = 5 V or 18 V; INT_EN = VDD
-1 -1 6 3 -1 -
General Purpose Inputs LOW-level input voltage HIGH-level input voltage input current HIGH-level input current input leakage current input capacitance LOW-level output current GPI recommended maximum current; VI > 5.5 V; with series resistor Rs each input; VI = VDD VI = 17 V; 100 k series resistor VI = VSS or VDD VDD = 4.5 V; VOL = 0.4 V VDD = 2.5 V; VOL = 0.4 V HIGH-level output current VOH = VDD output capacitance LOW-level input voltage HIGH-level input voltage HIGH-level input current LOW-level output current SDIN; VI = VDD = 5.5 V SDOUT; VOL = 0.4 V VDD = 4.5 V VDD = 2.5 V IOH HIGH-level output current SDOUT; VOH = VDD - 0.5 V VDD = 4.5 V VDD = 2.5 V Ci Co
[1] [2] [3]
[3]
0.4VDD V 100 +1 +1 5.0 +1 5 V A A A pF mA mA A pF
0.7VDD -
Interrupt output
SPI and control 0.3VDD V 5.5 40 5 6 V A mA mA mA mA pF pF 0.7VDD 5 3 5 3 -
input capacitance output capacitance
VI = VSS or VDD SDOUT; CS = VDD
VDD must be lowered to 0.2 V for at least 5 s in order to reset device. Minimum VIL is 2.0 V at VDD = 4.5 V. For GPI pin voltages > 5.5 V, see Section 7.3.
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
15 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
11. Dynamic characteristics
Table 6. Dynamic characteristics VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +125 C; unless otherwise specified. Symbol fmax tr tf tWH tWL tSPILEAD tSPILAG tsu(SDIN) th(SDIN) ten(SDOUT) tdis(SDOUT) tv(SDOUT) tsu(SCLK) th(SCLK) tPOR trel(int) tv(INT_N) Parameter maximum input clock frequency rise time fall time pulse width HIGH pulse width LOW SPI enable lead time SPI enable lag time SDIN set-up time SDIN hold time SDOUT enable time SDOUT disable time SDOUT valid time SCLK set-up time SCLK hold time power-on reset pulse time interrupt release time valid time on pin INT SDOUT; 10 % to 90 % at 5 V SDOUT; 90 % to 10 % at 5 V SCLK SCLK CS falling edge to SCLK rising edge SCLK falling edge to CS rising edge SDIN to SCLK falling edge from SCLK falling edge from CS LOW to SDOUT low-impedance; Figure 17 from rising edge of CS to SDOUT high-impedance; Figure 17 from rising edge of SCLK; Figure 18 SCLK falling to CS falling SCLK rising after CS rising time before CS is active after VDD > VPOR after CS going LOW; Figure 19 after INn changes or INT_EN goes HIGH Conditions Min 50 50 50 50 20 30 50 50 Typ 35 25 Max 5 60 50 55 85 55 250 500 100 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CS tsu(SCLK) tSPILEAD SCLK 50 % tsu(SDIN) tWH tWL 50 % th(SDIN) MSB in ten(SDOUT) high-impedance SDOUT trel(int) INT
002aac428
tSPILAG
th(SCLK)
SDIN
tv(SDOUT) MSB out
tdis(SDOUT)
Fig 14. Timing diagram
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
16 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
2.5 V VDD VPOR 0V
CS
SCLK
SDOUT tPOR
MSB out
MSB - 1
002aad158
Fig 15. AC waveform for tPOR timing
CS
INn
STATE 0
STATE 1
STATE 0
INT_EN tv(INT_N) INT trel(int) trel(int)
002aad159
tv(INT_N)
Fig 16. AC waveform for INT timing
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
17 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
12. Test information
VDD open VDD PULSE GENERATOR VI DUT
RT CL 50 pF 10 k
VO
RL 10 k
002aac580
Fig 17. Test circuitry for enable/disable times, SDOUT (ten(SDOUT) and tdis(SDOUT))
VDD PULSE GENERATOR VI DUT
RT CL 50 pF
VO
002aac581
Fig 18. Test circuitry for switching times, SDOUT (tv(SDOUT))
VDD VDD PULSE GENERATOR VI DUT
RT CL 50 pF RL 10 k
VO
002aac582
Fig 19. Test circuitry for switching times, INT
RL = load resistance. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators.
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
18 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
13. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 20. Package outline SOT137-1 (SO24)
PCA9701_PCA9702_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
19 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 21. Package outline SOT355-1 (TSSOP24)
PCA9701_PCA9702_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
20 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 22. Package outline SOT403-1 (TSSOP16)
PCA9701_PCA9702_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
21 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm
SOT994-1
D
B
A
terminal 1 index area E A A1 c
detail X
e1 1/2 e e
7
b
12
v w
M M
CAB C
C y1 C y
L
6 13
e
Eh 1/2 e
1
e2
18
terminal 1 index area
24
19
Dh
X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.8 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT994-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-02-07 07-03-03
Fig 23. Package outline SOT994-1 (HWQFN24)
PCA9701_PCA9702_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
22 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
PCA9701_PCA9702_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
23 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 7 and 8
Table 7. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 8. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24.
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
24 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
15. Abbreviations
Table 9. Acronym ASSP CAN CDM DUT ECU ESD GPI HBM HS-CAN LIN LSB MM MSB PCB PPAP RC SBC SPI C
PCA9701_PCA9702_3
Abbreviations Description Application Specific Standard Product Controller Area Network Charged-Device Model Device Under Test Electronic Control Unit ElectroStatic Discharge General Purpose Input Human Body Model High-Speed Controller Area Network Local Interconnect Network Least Significant Bit Machine Model Most Significant Bit Printed-Circuit Board Production Part Approval Process Resistor-Capacitor network System Basis Chip Serial Peripheral Interface microcontroller
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
25 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
16. Revision history
Table 10. Revision history Release date Data sheet status Product data sheet Change notice Supersedes PCA9701_PCA9702_2 Document ID Modifications:
PCA9701_PCA9702_3 20081203
*
Section 1 "General description": - 1st paragraph, 3rd sentence: appended "(minimum threshold of 2 V at 4.5 V node)" - 3rd paragraph, 2nd sentence changed from "... reverse battery, and load dump conditions" to "... reverse battery, 27 V jump start and 40 V load dump conditions" - 4th paragraph: added "(AEC-Q100 qualification available)" - added (new) 5th paragraph
*
Section 2 "Features": - added (new) 3rd bullet item - 10th bullet: deleted "INT_EN is 7.5 kV"; changed from "600 V MM per JEDS22-A115" to "350 V MM per AEC-Q100"
* *
Section 3 "Applications": added new 1st and 6th bullets Table 1 "Ordering information": - added Type number PCA9701PW/Q100 - added Table note [1] and its reference
* * * *
Section 7 "Functional description", 1st paragraph, 2nd sentence changed from "... reverse battery, or load dump conditions" to ... reverse battery, 27 V jump start or 40 V load dump conditions" Table 3 "Interrupt output function truth table": INT column: appended "output" to column heading; changed "high-Z" to "H" (3 places); added Table note [2] and its reference Added Section 7.3.1 "VIL, VIH and switching points" Section 8 "Application design-in information": - Figure 8 "Typical application" moved to (new) Section 8.1 "General application" - added Section 8.2
*
Table 5 "Static characteristics": - sub-section "General Purpose Inputs": VIL Max value changed from "0.3VDD" to "0.4VDD"; added (new) Table note [2] - sub-section "General Purpose Inputs": Ci Typ value changed from "1.0 pF" to "2.0 pF"; Ci Max value changed from "2.5 pF" to "5.0 pF" - sub-section "Interrupt output": changed Co Max value from "4 pF" to "5 pF" - sub-section "SPI and control": Ci Max value changed from "4 pF" to "5 pF" - Table note [1]: added phrase "for at least 5 s"
* *
Figure 15 "AC waveform for tPOR timing" modified updated soldering information Product data sheet Objective data sheet PCA9701_PCA9702_1 -
PCA9701_PCA9702_2 20070829 PCA9701_PCA9702_1 20070323
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
26 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9701_PCA9702_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 3 December 2008
27 of 28
NXP Semiconductors
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.2 7.3 7.3.1 8 8.1 8.2 8.2.1 8.2.1.1 8.2.1.2 8.2.1.3 8.2.2 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 SPI bus operation . . . . . . . . . . . . . . . . . . . . . . . 6 CS - chip select. . . . . . . . . . . . . . . . . . . . . . . . . 6 SCLK - serial clock input. . . . . . . . . . . . . . . . . . 6 SDIN - serial data input . . . . . . . . . . . . . . . . . . 6 SDOUT - serial data output . . . . . . . . . . . . . . . 6 Register access timing . . . . . . . . . . . . . . . . . . . 7 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 7 General Purpose Inputs . . . . . . . . . . . . . . . . . . 8 VIL, VIH and switching points. . . . . . . . . . . . . . . 9 Application design-in information . . . . . . . . . 10 General application. . . . . . . . . . . . . . . . . . . . . 10 Automotive application . . . . . . . . . . . . . . . . . . 10 SBC wake port extension with cyclic biasing . 11 UJA106x with PCA9701, standby . . . . . . . . . . 11 UJA106x with PCA9701, sleep. . . . . . . . . . . . 12 UJA107x with PCA9701, standby . . . . . . . . . . 13 Application examples including switches to battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 Static characteristics. . . . . . . . . . . . . . . . . . . . 15 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Soldering of SMD packages . . . . . . . . . . . . . . 23 Introduction to soldering . . . . . . . . . . . . . . . . . 23 Wave and reflow soldering . . . . . . . . . . . . . . . 23 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 Legal information. . . . . . . . . . . . . . . . . . . . . . . 27 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 18 19 Contact information . . . . . . . . . . . . . . . . . . . . 27 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 December 2008 Document identifier: PCA9701_PCA9702_3

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